Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.

A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design

Optimising bandwidth over deep sub-micron interconnect.

In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When relatively long wires are placed in parallel, it is essential to include the effects of cross-talk on delay. In a parallel wire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Repeater insertion depending on whether it is optimal or constrained, affects the delay in different ways. Considering all these effects we show that there is a clear optimum configuration for the wires which maximises the total bandwidth. Our analysis is valid for lossy interconnects as are typical of wires in DSM technologies

Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

A global wire planning scheme for Network-on-Chip.

As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed

Before the Morning After

This paper presents a wearable biopatch prototype for body surface potential measurement. It combines three key technologies, including mixed-signal system on chip (SoC) technology, inkjet printing technology, and anisotropic conductive adhesive (ACA) bonding technology. An integral part of the biopatch is a low-power low-noise SoC. The SoC contains a tunable analog front end, a successive approximation register analog-to-digital converter, and a reconfigurable digital controller. The electrodes, interconnections, and interposer are implemented by inkjet-printing the silver ink precisely on a flexible substrate. The reliability of printed traces is evaluated by static bending tests. ACA is used to attach the SoC to the printed structures and form the flexible hybrid system. The biopatch prototype is light and thin with a physical size of 16 cm x 16 cm. Measurement results show that low-noise concurrent electrocardiogram signals from eight chest points have been successfully recorded using the implemented biopatch.QC 20130805. Updated from accepted to published.</p